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What specifications are needed for card edge connectors in AI/ML systems?

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Card edge connectors connect peripheral devices or expansion cards to a host system. They provide a reliable interface for data transfer and power delivery, facilitating the integration of artificial intelligence (AI) components into a system. They support AI and machine learning (ML) on the edge, in the cloud, and in hyperscale data centers.

This article reviews three important specifications for card edge connectors in AI/ML systems: the widely adopted M.2 specification, the newer Enterprise and Datacenter Standard Form Factor (EDSFF), and the Open Compute Project network interface card (OCP NIC) 3.0 specifications.

Like mini-peripheral Component Interconnect Express (mPCIe) connectors, M.2 connectors support various signal interfaces and storage protocols and are designed to maximize the use of the PCIe bus. M.2 connectors are available that support PCIe 3.0, PCIe 4.5, PCIe 5.0, Serial ATA (SATA 3.0), and SuperSpeed USB.

M.2 connectors support the bandwidth AI/ML accelerators and solid-state drives (SSDs) need. They are described by their dimensions and keying. For example, a 2260 M.2 module measures 22 mm wide and 60 mm long. In addition, M.2 modules have recesses at certain points on the plug connector strip to prevent misinsertions. Common key formats include B, M, A, and E, together with B+M and A+E (Figure 1).

Figure 1. Examples of M.2 form factors, from left to right: 1630 Key E, 2230 Key E, 3030 Key A, 2242 Key B+M, 3042 Key A, 2260 Key M, 2280 Key B+M. (Image: Delock)

Benefits of M.2 for AI/ML

  • Supports high-density solutions, the smallest M.2 devices are 18% smaller than the smallest mPCIe devices
  • Flexibility, since M.2 ports are available, can support multiple sizes of M.2 cards
  • Low power, limited to 7 W or less
  • High speed, for example, M.2 slots can include two to four PCIe lanes, with PCIe 4.0 delivering a 16 Gb/s transfer rate on each lane

PCIe M.2 Gen 5 connectors are available with 67 contacts on a 0.50 mm pitch. These connectors support single- and double-sided modules. They require less board space compared to mPCIe connectors (Figure 2). Other features include:

  • Variety of connector heights and keying options
  • Accept angled insertion of modules
  • Choice of right-angle or vertical orientations
Figure 2. These PCIe M.2 Gen 5 Connectors have 67 contacts on a 0.50 mm pitch. (Image: Amphenol)

EDSFF for storage

The EDSFF specification was created by the Storage Networking Industry Association SSD small form factor (SNIA SFF) Technology Affiliate group to address the needs for data center storage. It was designed to address the limitations of legacy form factors by designing a new specification optimized for NAND flash memory and other devices. Benefits of the EDSFF connector specification include:

  • Improved signal integrity to support PCIe 5.0 and PCIe 6.0
  • Single connector standard supports all EDSFF configurations
  • Flexibility to support chassis and backplane applications
  • Higher power up to 70 W

OPC NIC 3.0 for more power

The OCP NIC 3.0 specification includes three form factors: Small Form Factor (SFF), tall small form factor (TSFF), and large form factor (LFF). The SFF and TSFF can include up to 16 PCIe lanes, while the LFF can include up to 32 PCIe lanes (Figure 3). The SFF and TSFF configurations can handle up to 80W to the NIC, while the dual connector LFF configuration can handle up to 150 W.

Figure 3. Configurations and basic specifications of OCP NIC 3.0 SFF/TSFF (left) and LFF (right). (Image: Serve the Home)

OCP NIC 3.0 works with PCIe Gen 4 (16 Gb/s) on the baseboard and OCP NIC 3.0 card and is electrically with PCIe Gen 5 (32 Gb/s). It can handle up to 32 lanes of PCIe per OCP NIC 3.0 card and supports single-host, multi-root complex, and multi-host environments. The next iterations are expected to support differential pairs up to 64 G PAM4 and the ability to upgrade to 112 G PAM4 and 224 G PAM4 further in the future.

Summary

Designers have several choices of card edge standards for AI/ML systems. For deployments on the edge, M.2 connectivity is available in a range of configurations. It can support high-density and low-power solutions up to 7 W. EDSFF was developed specifically to support the needs of SSDs and other storage technologies. For higher power and larger NICs, designers can turn to OCP NIC 3.0, which can handle up to 150 W to power AI/ML accelerators, large SSDs, and similar applications.

References

EDSFF – A New SSD Form Factor for Next Gen Servers and Storage, Kioxia
How Artificial Intelligence (AI) Is Transforming NVMe SSDs, Microchip
PCIe M.2 Gen 5 Card Edge Connectors, Amphenol
The M.2 interface, Delock
Unlocking the Power of Cloud Storage and Compute with EDSFF SSDs, Solidigm
What Is The M.2 Expansion Slot?, Premio

Filed Under: Connector Tips

 

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