Developers of high-end semiconductor products that face manufacturing limitations with respect to die sizes are investing in 3D stacked die technology. These advanced designs already push current design-for-test (DFT) solutions to the limits: tool run time, on-chip area demand, test pattern count, and test time.

The next major step for improving system-in-package technology is 3D die stacking and packaging. While there are multiple methods of 3D die stacking, they share the common goals of using smaller, high-yield dies that are vertically stacked. This strategy can alleviate many of the test challenges for large 2D or 2.5D devices.

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